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ltc3601 1 3601fa typical application features applications description 1.5a, 15v monolithic synchronous step-down regulator n distributed power systems n lithium-ion battery-powered instruments n point-of-load power supply l , lt, ltc, ltm, burst mode, linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611. ef? ciency and power loss vs load current n 4v to 15v operating input voltage range n 1.5a output current n up to 96% ef? ciency n very low duty cycle operation: 5% at 2.25mhz n adjustable switching frequency: 800khz to 4mhz n external frequency synchronization n current mode operation for excellent line and load transient response n user selectable burst mode ? (no load i q = 300a) or forced continuous operation n 0.6v reference allows low output voltages n short-circuit protected n output voltage tracking capability n programmable soft-start n power good status output n available in small, thermally enhanced, 16-pin qfn (3mm 3mm) and msop packages the ltc ? 3601 is a high ef? ciency, monolithic synchronous buck regulator using a phase-lockable controlled on-time, current mode architecture capable of supplying up to 1.5a of output current. the operating supply voltage range is from 4v to 15v, making it suitable for a wide range of power supply applications. the operating frequency is programmable from 800khz to 4mhz with an external resistor enabling the use of small surface mount inductors. for switching noise sensitive applications, the ltc3601 can be externally synchronized over the same frequency range. an internal phase-locked loop aligns the on-time of the top power mosfet to the internal or external clock. this unique constant frequency/ controlled on-time architecture is ideal for high step-down ratio applications that demand high switching frequencies and fast transient response. the ltc3601 offers two operational modes: burst mode operation and forced continuous mode to allow the user to optimize output voltage ripple, noise, and light load ef? ciency for a given application. maximum light load ef? ciency is achieved with the selection of burst mode operation while forced continuous mode provides minimum output ripple and constant frequency operation. v in run pgood track ltc3601 pgnd sgnd boost intv cc ith rt mode/sync sw v on fb 2.2f 10pf 0.1f 22f v out 3.3v 1.5a 180k 40k 3601 ta01a 2.2h 22f v in 4v to 15v load current (a) 30 efficiency (%) power loss (mw) 90 100 20 10 80 50 70 60 40 0.001 0.1 1 10 3601 ta01b 0 1000 100 10 1 0.01 v in = 5v v in = 12v
ltc3601 2 3601fa absolute maximum ratings (note 1) 16 15 14 13 5 6 7 8 top view 17 ud package 16-lead (3mm s 3mm) plastic qfn 9 10 11 12 4 3 2 1 mode/sync pgood sw sw ith fb rt sgnd v in v in run track nc boost intv cc v on t jmax = 125c, 1 2 3 4 5 6 7 8 sw sw pgnd pgnd boost intv cc v on rt 16 15 14 13 12 11 10 9 pgood mode/sync v in v in run track i th fb top view 17 mse package 16-lead plastic msop t max 125c
ltc3601 3 3601fa electrical characteristics symbol parameter conditions min typ max units v vin input supply range l 415v i q input dc supply current forced continuous operation sleep current shutdown mode = 0v mode = intv cc , v fb > 0.6v run = 0v 700 300 14 1000 500 25 a a a v fb feedback reference voltage l 0.594 0.600 0.606 v 6 v linereg reference voltage line regulation v vin = 4v to 15v 0.01 %/v 6 v loadreg output voltage load regulation ith = 0.6v to 1.6v 0.1 % i fb feedback pin input current v fb = 0.6v 30 na g m(ea) error ampli? er transconductance ith = 1.2v 2.0 ms t on(min) minimum on-time v on = 1v, v in = 4v 20 ns t off(min) minimum off-time v in = 6v 40 60 ns i lim valley switch current limit 1.7 2.2 2.8 a f osc oscillator frequency v rt = intv cc r rt = 160k r rt = 80k 1.4 1.7 3.4 2 2 4 2.6 2.3 4.6 mhz mhz mhz r ds(on) top switch on-resistance 130 m bottom switch on-resistance 100 m v vin-ov v in overvoltage lockout threshold v in rising v in falling l l 16.8 15.8 17.5 16.5 18 17 v v v intvcc intv cc voltage 4v < v in < 15v 3.15 3.3 3.45 v 6 intv cc intv cc load regulation (note 4) i intvcc = 0ma to 20ma 0.6 % v uvlo intv cc undervoltage lockout threshold intv cc rising, v in = intv cc intv cc falling, v in = intv cc 2.75 2.45 2.9 v v v run run threshold run rising run falling l l 1.21 0.97 1.25 1.0 1.29 1.03 v v i run(lkg) run leakage current v vin = 15v 0 3 a v fb_gb pgood good-to-bad threshold fb rising fb falling 8 C8 10 C10 % % v fb_bg pgood bad-to-good threshold fb rising fb falling C3 3 C5 5 % % t pgood power good filter time 20 40 s r pgood pgood pull-down resistance 10ma load 15 i sw(lkg) switch leakage current v run = 0v 0.01 1 a t ss internal soft-start time v fb from 10% to 90% full scale 400 700 s v fb_track track pin track = 0.3v 0.28 0.3 0.315 mv i track track pull-up current 1.4 a v mode/ sync mode threshold voltage mode v ih mode v il l l 1.0 0.4 v v sync threshold voltage sync v ih l 0.95 v i mode mode input current mode = 0v mode = intv cc C1.5 1.5 a a the l denotes the speci? cations which apply over the full operating junction temperature range, otherwise speci? cations are at t a = 25c. v vin = 12v, unless otherwise speci? ed.
ltc3601 4 3601fa typical performance characteristics ef? ciency vs load current burst mode operation ef? ciency vs load current forced continuous mode ef? ciency vs frequency forced continuous mode reference voltage vs temperature electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3601 is tested under pulsed load conditions such that t j t a . the ltc3601e is guaranteed to meet speci? cations from 0c to 85c junction temperature. speci? cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3601i is guaranteed over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature consistent with these speci? cations is determined by speci? c operating ef? ciency vs input voltage burst mode operation conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the following formula: t j = t a + (p d ? e ja ) where e ja = 45c/w for the qfn package and e ja = 38c/w for the msop package. note 4: maximum allowed current draw when used as a regulated output is 5ma. this supply is only intended to provide additional dc load current as needed and not intended to regulate large transient or ac behavior as these waveforms may impact ltc3601 operation. ef? ciency vs load current t a = 25c, v in = 12v, f o = 1mhz, l = 2.2h unless otherwise noted. load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.001 0.1 1 10 3601 g01 0 0.01 v in = 4v v in = 8v v in = 12v v out = 1.8v load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.001 0.1 1 10 3601 g02 0 0.01 v in = 4v v in = 8v v in = 12v v out = 1.8v load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.001 0.1 1 10 3601 g03 0 0.01 v out = 3.3v v out = 5v burst forced continuous input voltage (v) 4 efficiency (%) 75 80 85 10 14 3601 g04 70 65 60 68 12 90 95 100 16 i load = 500ma i load = 100ma v out = 1.8v figure 7 circuit i load = 1.5a i load = 10ma frequency (mhz) 0.5 80 efficiency (%) 82 84 86 88 90 92 1.0 1.5 2.0 2.5 3601 g05 3.0 l = 2.2h v out =1.8v i load = 500ma l = 1h temperature (c) C50 C25 0.595 v ref (v) 0.599 0.605 0 50 75 3601 g06 0.597 0.603 0.601 25 100 125
ltc3601 5 3601fa typical performance characteristics quiescent current vs supply voltage oscillator frequency vs temperature r ds(on) vs temperature switch leakage vs temperature t a = 25c, v in = 12v, f o = 1mhz, l = 2.2h unless otherwise noted. temperature (c) C50 C25 0 r ds(on) (m) 80 200 0 50 75 3601 g07 40 160 120 25 100 125 top switch r ds(on) bottom switch r ds(on) temperature (c) C50 switch leakage (na) 4000 5000 6000 25 75 3601 g08 3000 2000 C25 0 50 100 125 1000 0 top switch bottom switch v ds = 12v supply voltage (v) 4 220 quiescent current (a) 260 300 340 380 6 8 10 12 3601 g09 14 16 temperature (c) C50 frequency variation (%) 1.5 25 3601 g10 0 C1.0 C25 0 50 C1.5 C2.0 2.0 1.0 0.5 C0.5 75 100 125 bottom switch current limit vs temperature load regulation temperature (c) C50 2.0 2.5 3.5 25 75 3601 g11 1.5 1.0 C25 0 50 100 125 0.5 0 3.0 i lim (a) i load (ma) 0 1.2 1.0 0.8 0.6 0.4 0.2 0 C0.2 750 1250 3601 g21 250 500 1000 1500 v out /v out (%) burst mode operation forced continuous oscillator internal set frequency vs temperature track pull-up current vs temperature temperature (c) C50 frequency (mhz) 2.25 2.50 2.75 25 75 3601 g22 2.00 1.75 C25 0 50 100 125 1.50 1.25 rt = intv cc temperature (c) C50 1.4 1.6 2.0 25 75 3601 g23 1.2 1.0 C25 0 50 100 125 0.8 0.6 1.8 i track (a)
ltc3601 6 3601fa typical performance characteristics start-up from shutdown burst mode operation start-up from shutdown forced continuous mode load step burst mode operation load step forced continuous mode short-circuit waveforms forced continuous mode t a = 25c, v in = 12v, f o = 1mhz, l = 2.2h unless otherwise noted. run 2v/div pgood 5v/div i l 1a/div 200s/div 3601 g15 v in = 12v v out = 1.8v i load = 20ma v out 2v/div run 2v/div i l 1a/div 200s/div 3601 g16 v in = 12v v out = 1.8v i load = 1.5a v out 1v/div v out 100mv ac coupled i load 1a/div 10s/div 3601 g17 v in = 12v v out = 1.8v i load = 150ma to 1.5a i l 1a/div v out 100mv ac coupled i load 1a/div 10s/div 3601 g18 v in = 12v v out = 1.8v i load = 150ma to 1.5a i l 1a/div v out 1v/div pgood 2v/div 100s/div 3601 g19 v in = 12v v out = 1.8v i l 2a/div start-up into pre-biased output (1v pre-bias) burst mode operation v out 1v/div run 10v/div pgood 5v/div 1ms/div 3601 g20 v in = 12v v out = 1.8v i load = 5ma i l 1a/div output voltage vs time burst mode operation sw 5v/div i l 1a/div 2s/div 3601 g12 v in = 12v v out = 1.8v i load = 100ma v out 20mv/div ac coupled output voltage vs time forced continuous mode sw 5v/div i l 1a/div 2s/div 3601 g13 v in = 12v v out = 1.8v i load = 100ma v out 20mv/div ac coupled output tracking 2ms/div 3601 g14 v in = 12v v out = 1.8v r load = 36 v out v fb track
ltc3601 7 3601fa pin functions (qfn/mse) mode/sync (pin 1/pin 15): mode selection and external synchronization input pin. this pin places the ltc3601 into forced continuous operation when tied to ground. high ef? ciency burst mode operation is enabled by either ? oating this pin or by tying this pin to intv cc . when driven with an external clock, an internal phase-locked loop will synchronize the phase and frequency of the internal oscil- lator to that of the incoming clock signal. during external clock synchronization, the ltc3601 will default to forced continuous operation. pgood (pin 2/pin 16): open-drain power good output pin. pgood is pulled to ground when the voltage at the fb pin is not within 8% (typical) of the internal 0.6v reference. pgood becomes high impedance once the voltage at the fb pin returns to within 5% (typical) of the internal reference. sw (pins 3, 4/pins 1, 2): switch node output pin. con- nect this pin to the sw side of the external inductor. the normal operation voltage swing of this pin ranges from ground to pv in . boost (pin 6/pin 5): boosted floating driver supply pin. the (+) terminal of the external bootstrap capacitor connects to this pin while the (C) terminal connects to the sw pin. the normal operation voltage swing of this pin ranges from a diode voltage drop below intv cc up to pv in + intv cc . intv cc (pin 7/pin 6): internal 3.3v regulator output pin. this pin should be decoupled to pgnd with a low esr ceramic capacitor of 1f or more. v on (pin 8/pin 7): on-time voltage input pin. this pin sets the voltage trip point for the on-time comparator. connect this pin to the regulated output to make the on-time pro- portional to the output voltage when v out 6v. if v out > 6v, switching frequency may become higher than the set frequency. the pin impedance is normally 180k. sgnd (pin 9/pin 17): signal ground pin. this pin should have a low noise connection to reference ground. the feedback resistor network, external compensation network and rt resistor should be connected to this ground. in the mse package, this pin must be soldered to the pcb to provide a good thermal contact to the pcb. rt (pin 10/pin 8): oscillator frequency program pin. con- nect an external resistor, between 80k to 400k, from this pin to sgnd to program the ltc3601 switching frequency from 800khz to 4mhz. when rt is tied to intv cc , the switching frequency will default to 2mhz. fb (pin 11/pin 9): output voltage feedback pin. input to the error ampli? er that compares the feedback voltage to the internal 0.6v reference voltage. connect this pin to the appropriate resistor divider network to program the desired output voltage. ith (pin 12/pin 10): error ampli? er output and switching regulator compensation pin. connect this pin to appro- priate external components to compensate the regulator loop frequency response. connect this pin to intv cc to use the default internal compensation. track (pin 13/pin 11): output voltage tracking and soft- start input pin. forcing a voltage below 0.6v on this pin overrides the internal reference input to the error ampli? er. the ltc3601 will servo the fb pin to the track voltage under this condition. above 0.6v, the tracking function stops and the internal reference resumes control of the error ampli? er. an internal 1.4a pull-up current from intv cc allows a soft-start function to be implemented by connecting an external capacitor between this pin and ground. see applications information section for more details. run (pin 14/pin 12): regulator enable pin. enables chip operation by applying a voltage above 1.25v. a voltage below 1v on this pin places the part into shutdown. do not ? oat this pin. v in (pins 15, 16/pins 13, 14): main power supply input pins. these pins should be closely decoupled to pgnd with a low esr capacitor of 10f or more. pgnd (pin 17/pins 3, 4): power ground pin. the (C) terminal of the input bypass capacitor, c in , and the (C) terminal of the output capacitor, c out , should be tied to this pin with a low impedance connection. in the qfn package this pin must be soldered to the pcb to provide low impedance electrical contact to ground and good thermal contact to the pcb.
ltc3601 8 3601fa functional block diagram C + + C + C + v in v in 15k q6 run switch logic and anti- shoot through bg on q1 q2 0.48v 1.25v run ea internal soft-start ss q4 track c ss 3605 bd sgnd r2 r1 run pgnd pgood intv cc fb sw tg v in c in boost sense + sense C C + C + ov 0.648v C + 0.3v foldback foldback disabled at start-up uv 0.552v 180k v on v on int vcc m2 m1 l1 c out intv cc ith r c c c1 c vcc c boost C + C + 1.4a i thb i cmp i rev 3.3v reg i on controller osc pll-sync osc r 0.6v ref sq i on mode/sync r rt rt t on = v von i ion a v = 1 6v
ltc3601 9 3601fa operation the ltc3601 is a current mode, monolithic, step-down regulator capable of providing up to 1.5a of output current. its unique controlled on-time architecture allows extremely low step-down ratios while maintaining a constant switch- ing frequency. part operation is enabled by raising the voltage on the run pin above 1.25v nominally. main control loop in normal operation the internal top power mosfet is turned on for a ? xed interval determined by an internal one-shot timer (on signal in the block diagram). when the top power mosfet turns off, the bottom power mosfet turns on until the current comparator, i cmp , trips, thus restarting the one-shot timer and initiating the next cycle. the inductor current is monitored by sensing the voltage drop across the sw and pgnd nodes of the bottom power mosfet. the voltage at the ith pin sets the i cmp comparator threshold corresponding to the induc- tor valley current. the error ampli? er ea adjusts this ith voltage by comparing an internal 0.6v reference to the feedback signal, v fb , derived from the output voltage. if, for example, the load current increases, the feedback voltage will decrease relative to the internal 0.6v reference. the ith voltage then rises until the average inductor current matches that of the load current. the operating frequency is determined by the value of the rt resistor, which programs the current for the internal oscillator. an internal phase-locked loop servos the switch- ing regulator on-time to track the internal oscillator edge and force a constant switching frequency. a clock signal can be applied to the sync/mode pin to synchronize the switching frequency to an external source. the regulator defaults to forced continuous operation once the clock signal is applied. at low load currents the inductor current can drop to zero or become negative. if the ltc3601 is con? gured for burst mode operation, this inductor current condition is detected by the current reversal comparator, i rev , which in turn shuts off the bottom power mosfet and places the part into a low quiescent current sleep state resulting in discontinuous operation and increased ef? ciency at low load currents. both power mosfets will remain off with the part in sleep and the output capacitor supplying the load current until the ith voltage rises suf? ciently to initi- ate another cycle. discontinuous operation is disabled by tying the mode/sync pin to ground placing the ltc3601 into forced continuous mode. during forced continuous mode, continuous synchronous operation occurs regard- less of the output load current. power good status output the pgood open-drain output will be pulled low if the regulator output exits a 8% window around the regulation point. this condition is released once regulation within a 5% window is achieved. to prevent unwanted pgood glitches during transients or dynamic v out changes, the ltc3601 pgood falling edge includes a ? lter time of ap- proximately 40s. v in overvoltage protection in order to protect the internal power mosfet devices against transient voltage spikes, the ltc3601 constantly monitors the v in pin for an overvoltage condition. when v in rises above 17.5v, the regulator suspends operation by shutting off both power mosfets. once v in drops below 16.5v, the regulator immediately resumes normal operation. the regulator does not execute its soft-start function when exiting an overvoltage condition. short-circuit protection foldback current limiting is provided in the event the output is inadvertently shorted to ground. during this condition the internal current limit (i lim ) will be lowered to approximately one-third its normal value. this feature reduces the heat dissipation in the ltc3601 during short- circuit conditions and protects both the ic and the input supply from any potential damage.
ltc3601 10 3601fa applications information a general ltc3601 application circuit is shown on the ? rst page of this data sheet. external component selection is largely driven by the load requirement and begins with the selection of the inductor l. once the inductor is chosen, the input capacitor, c in , the output capacitor, c out , the internal regulator capacitor, c intvcc , and the boost capacitor, c boost , can be selected. next, the feedback resistors are selected to set the desired output voltage. finally, the remaining option- al external components can be selected for functions such as external loop compensation, track/soft-start, externally programmed oscillator frequency and pgood. operating frequency selection of the operating frequency is a trade-off between ef? ciency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequencies improves ef? ciency by reducing internal gate charge losses but requires larger inductance values and/or capacitance to maintain low output ripple voltage. the operating frequency, f o , of the ltc3601 is determined by an external resistor that is connected between the rt pin and ground. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator and can be calculated by using the following equation: r e f rt o = 32 11 . where r rt is in and f o is in hz. connecting the rt pin to intv cc will default the converter to f o = 2mhz; however, this switching frequency will be more sensitive to process and temperature variations than when using a resistor on rt (see typical performance characteristics). inductor selection for a given input and output voltage, the inductor value and operating frequency determine the inductor ripple current. more speci? cally, the inductor ripple current decreases with higher inductor value or higher operating frequency according to the following equation: i l = v out f? l 1C v out v i n where 6 i l = inductor ripple current, f = operating frequency and l = inductor value. a trade-off between component size, ef? ciency and operating frequency can be seen from this equation. accepting larger values of 6 i l allows the use of lower value inductors but results in greater core loss in the inductor, greater esr loss in the output capaci- tor, and larger output ripple. generally, highest ef? ciency operation is obtained at low operating frequency with small ripple current. a reasonable starting point for setting the ripple current is about 40% of i out(max) . note that the largest ripple current occurs at the highest v in . to guarantee the ripple current does not exceed a speci? ed maximum the inductance should be chosen according to: l = v out f? i l(max ) 1C v out v in(max ) once the value for l is known the type of inductor must be selected. actual core loss is independent of core size for a ? xed inductor value but is very dependent on the inductance selected. as the inductance increases, core loss decreases. unfortunately, increased inductance requires more turns of wire leading to increased copper loss. ferrite designs exhibit very low core loss and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core materials saturate hard, meaning the induc- tance collapses abruptly when the peak design current is rt (k) 0 0 frequency (khz) 1000 2000 3000 4000 6000 100 200 300 400 3601 f01 500 600 5000 figure 1. switching frequency vs rt
ltc3601 11 3601fa applications information exceeded. this collapse will result in an abrupt increase in inductor ripple current, so it is important to ensure the core will not saturate. different core materials and shapes will change the size/current and price/current relationship of an induc- tor. toroid or shielded pot cores in ferrite or permalloy materials are small and dont radiate much energy but generally cost more than powdered iron core inductors with similar characteristics. the choice of which style inductor to use mainly depends on the price versus size requirements and any radiated ? eld/emi requirements. new designs for surface mount inductors are available from toko, vishay, nec/tokin, cooper, coilcraft, tdk and wrth electronik. table 1 gives a sampling of available surface mount inductors. table 1. inductor selection table inductance (h) dcr (m) max current (a) dimensions (mm) height (mm) wrth electronik we-pd2 typ ms series 0.56 0.82 1.2 1.7 2.2 9.5 14 21 27 36 6.5 5.4 4.8 4 3.6 5.2 5.8 2 vishay ihlp-2020bz-01 series 0.47 0.68 1 2.2 8.8 12.4 20 50.1 11.5 10 7 4.2 5.2 5.5 2 toko de3518c series 0.56 1.2 1.7 24 30 35 3.3 2.4 2.1 3.5 3.7 1.8 sumida cdrh2d18/hp series 0.56 0.82 1.1 33 39 43 3.7 2.9 2.5 3.2 3.2 2 cooper sd18 series 0.47 0.82 1.2 1.5 2.2 20.1 24.7 29.4 34.5 39.8 3.58 3.24 2.97 2.73 2.55 5.5 5.5 1.8 coilcraft lps4018 series 0.56 1 2.2 30 40 70 4.8 2.8 2.7 4 41.7 tdk vls252012 series 0.47 1 1.5 2.2 56 88 126 155 3.3 2.4 2 1.8 2.5 21.2 c in and c out selection the input capacitance, c in , is needed to ? lter the trapezoidal wave current at the drain of the top power mosfet. to prevent large voltage transients from occurring a low esr input capacitor sized for the maximum rms current is recommended. the maximum rms current is given by: ii vvv v rms out max out in out in = () () C where i out(max) equals the maximum average output current. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even signi? cant deviations do not offer much relief. note that ripple cur- rent ratings from capacitor manufacturers are often based on only 2000 hours of life which makes it advisable to further de-rate the capacitor or choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet the require- ments of the design. for low input voltage applications suf? cient bulk input capacitance is needed to minimize transient effects during output load changes. even though the ltc3601 design includes an overvoltage protection circuit, care must always be taken to ensure input volt- age transients do not pose an overvoltage hazard to the part. the selection of c out is primarily determined by the effec- tive series resistance (esr) that is required to minimize voltage ripple and load step transients. the output ripple, 6 v out , is determined by: v out < i l esr + 1 8?f?c ou t the output ripple is highest at maximum input voltage since 6 i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic, and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer low esr but have lower capacitance density than other types. tantalum capacitors have the
ltc3601 12 3601fa applications information highest capacitance density, but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have signi? cantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long-term reliability. ceramic capacitors have excellent low esr characteristics and small footprints. their relatively low value of bulk capacitance may require multiple capacitors in parallel. using ceramic input and output capacitors higher value, lower cost ceramic capacitors are now available in small case sizes. their high voltage rating and low esr make them ideal for switching regulator applications. however, due to the self-resonant and high-q characteristics of some types of ceramic capacitors, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input, and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the v in input. at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. for a more detailed discussion, refer to application note 88. when choosing the input and output ceramic capacitors choose the x5r or x7r dielectric formulations. these dielectrics provide the best temperature and voltage characteristics for a given value and size. intv cc regulator bypass capacitor an internal low dropout (ldo) regulator produces a 3.3v supply voltage used to power much of the internal ltc3601 circuitry including the power mosfet gate drivers. the intv cc pin connects to the output of this regulator and must have a minimum of 1f of decoupling capacitance to ground. the decoupling capacitor should have low impedance electrical connections to the intv cc and pgnd pins to provide the transient currents required by the ltc3601. the user may connect a maximum load current of 5ma to this pin but must take into account the increased power dissipation and die temperature that results. furthermore, this supply is intended only to supply additional dc load currents as desired and not intended to regulate large transient or ac behavior this may impact ltc3601 operation. boost capacitor the boost capacitor, c boost , is used to create a voltage rail above the applied input voltage v in . speci? cally, the boost capacitor is charged to a voltage equal to approximately intv cc each time the bottom power mosfet is turned on. the charge on this capacitor is then used to supply the required transient current during the remainder of the switching cycle. when the top mosfet is turned on, the boost pin voltage will be equal to approximately v in + 3.3v. for most applications a 0.1f ceramic capacitor will provide adequate performance. output voltage programming the ltc3601 will adjust the output voltage such that v fb equals the reference voltage of 0.6v according to: v out = 0.6v 1 + r1 r 2 the desired output voltage is set by appropriate selection of resistors r1 and r2 as shown in figure 2. choosing large values for r1 and r2 will result in improved ef? ciency but may lead to undesirable noise coupling or phase margin reduction due to stray capacitances at the fb node. care should be taken to route the fb line away from any noise source, such as the sw line. to improve the frequency response of the main control loop a feedforward capacitor, c f , may be used as shown in figure 2. fb r1 r2 c f 3601 f02 v out sgnd ltc3601 figure 2. optional feedforward capacitor
ltc3601 13 3601fa applications information minimum off-time/on-time considerations the minimum off-time is the smallest amount of time that the ltc3601 can turn on the bottom power mosfet, trip the current comparator and turn the power mosfet back off. this time is typically 40ns. for the controlled on-time current mode control architecture, the minimum off-time limit imposes a maximum duty cycle of: dc f t max off min () () C? = () 1 where f is the switching frequency and t off(min) is the minimum off-time. if the maximum duty cycle is surpassed, due to a dropping input voltage for example, the output will drop out of regulation. the minimum input voltage to avoid this dropout condition is: v v ft in min out off min () () ? = < () 1 conversely, the minimum on-time is the smallest dura- tion of time in which the top power mosfet can be in its on state. this time is typically 20ns. in continuous mode operation, the minimum on-time limit imposes a minimum duty cycle of: dc f t min on min () () ? = () where t on(min) is the minimum on-time. as the equation shows, reducing the operating frequency will alleviate the minimum duty cycle constraint. in the rare cases where the minimum duty cycle is surpassed, the output voltage will still remain in regula- tion, but the switching frequency will decrease from its programmed value. this is an acceptable result in many applications, so this constraint may not be of critical importance in most cases, and high switching frequen- cies may be used in the design without any fear of severe consequences. as the sections on inductor and capacitor selection show, high switching frequencies allow the use of smaller board components, thus reducing the footprint of the application circuit. internal/external loop compensation the ltc3601 provides the option to use a ? xed internal loop compensation network to reduce both the required external component count and design time. the internal loop compensation network can be selected by connecting the ith pin to the intv cc pin. to ensure stability, it is recom- mended that the output capacitance be at least 47f when using internal compensation. alternatively, the user may choose speci? c external loop compensation components to optimize the main control loop transient response as desired. external loop compensation is chosen by simply connecting the desired network to the ith pin. suggested compensation component values are shown in figure 3. for a 2mhz application, an r-c network of 220pf and 13k provides a good starting point. the bandwidth of the loop increases with decreasing c. if r is increased by the same factor that c is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop. a 10pf bypass capacitor on the ith pin is recommended for the purposes of ? ltering out high frequency coupling from stray board capacitance. in addition, a feedforward capacitor c f can be added to improve the high frequency response, as previously shown in figure 2. capacitor c f provides phase lead by creating a high frequency zero with r1 which improves the phase margin. figure 3. compensation components ith r comp 13k c comp 220pf c byp 3601 f03 sgnd ltc3601
ltc3601 14 3601fa checking transient response the regulator loop response can be checked by observing the response of the system to a load step. when con? g- ured for external compensation, the availability of the ith pin not only allows optimization of the control loop behavior but also provides a dc coupled and ac ? ltered closed-loop response test point. the dc step, rise time, and settling behavior at this test point re? ect the systems closed-loop response. assuming a predominantly second order system, the phase margin and/or damping factor can be estimated by observing the percentage of overshoot seen at this pin. the ith external components shown in figure 3 will provide an adequate starting point for most applications. the series r-c ? lter sets the pole-zero loop compensation. the values can be modi? ed slightly, from approximately 0.5 to 2 times their suggested values, to optimize transient response once the ? nal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because their various types and values determine the loop feedback factor gain and phase. an output cur- rent pulse of 20% to 100% of full load current with a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop when observing the response of v out to a load step, the initial output voltage step may not be within the bandwidth of the feedback loop. as a result, the standard second order overshoot/dc ratio cannot be used to estimate phase margin. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. for a detailed explanation of optimizing the compensation components, including a review of control loop theory, refer to linear technology application note 76. as shown in figure 2 a feedforward capacitor, c f , may be added across feedback resistor r1 to improve the high frequency response of the system. capacitor c f provides phase lead by creating a high frequency zero with r1. applications information in some applications severe transients can be caused by switching in loads with large (>10f) input capacitors. the discharged input capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this output droop if the switch connecting the load has low resistance and is driven quickly. the solution is to limit the turn-on speed of the load switch driver. a hot swap? controller is designed speci? - cally for this purpose and usually incorporates current limit, short-circuit protection and soft-start functions. mode/sync operation the mode/sync pin is a multipurpose pin allowing both mode selection and operating frequency synchroniza- tion. connecting this pin to intv cc enables burst mode operation for superior ef? ciency at low load currents at the expense of slightly higher output voltage ripple. when the mode/sync pin is pulled to ground, forced continuous mode operation is selected creating the lowest ? xed output ripple at the expense of light load ef? ciency. the ltc3601 will detect the presence of the external clock signal on the mode/sync pin and synchronize the internal oscillator to the phase and frequency of the incoming clock. the presence of an external clock will place the ltc3601 into forced continuous mode operation. output voltage tracking and soft-start the ltc3601 allows the user to control the output voltage ramp rate by means of the track pin. from 0v to 0.6v the track pin will override the internal reference input to the error ampli? er forcing regulation of the feedback voltage to that seen at the track pin. when the voltage at the track pin rises above 0.6v, tracking is disabled and the feedback voltage will be regulated to the internal reference voltage. the voltage at the track pin may be driven from an ex- ternal source, or alternatively, the user may leverage the internal 1.4a pull-up current on track to implement
ltc3601 15 3601fa applications information a soft-start function by connecting a capacitor from the track pin to ground. the relationship between output rise time and track capacitance is given by: t ss = 430,000 c track a default internal soft-start timer forces a minimum soft- start time of 400s by overriding the track pin input during this time period. hence, capacitance values less than approximately 1000pf will not signi? cantly affect soft-start behavior. when using the track pin, the regulator defaults to burst mode operation until the output exceeds 80% of its ? nal value (v fb > 0.48v). once the output reaches this voltage, the operating mode of the regulator switches to the mode selected by the mode/sync pin as described above. during normal operation, if the output drops below 10% of its ? nal value (as it may when tracking down, for instance), the regulator will automatically switch to burst mode operation to prevent inductor saturation and improve track pin accuracy. output power good the pgood output of the ltc3601 is driven by a 15 (typical) open-drain pull-down device. this device will be turned off once the output voltage is within 5% (typical) of the target regulation point allowing the voltage at pgood to rise via an external pull-up resistor (100k typical). if the output voltage exits a 8% (typical) regulation window around the target regulation point the open-drain output will pull down with 15 output resistance to ground, thus dropping the pgood pin voltage. a ? lter time of 40s (typical) acts to prevent unwanted pgood output changes during v out transient events. as a result, the output voltage must be within the target regulation win- dow of 5% for 40s before the pgood pin is pulled high. conversely, the output voltage must exit the 8% regulation window for 40s before the pgood pin pulls to ground (see figure 4). ef? ciency considerations the percent ef? ciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the ef? ciency and which change would produce the most improvement. percent ef? ciency can be expressed as: % ef? ciency = 100% C (l1 + l2 + l3 +) where l1, l2, etc. are the individual loss terms as a per- centage of input power. although all dissipative elements in the circuit produce losses, three main sources account for the majority of the losses in the ltc3601: 1) i 2 r loss, 2) switching losses and quiescent current loss, 3) transition losses and other system losses. 1. i 2 r loss is calculated from the dc resistances of the internal switches, r sw , and external inductor, r l . in continuous mode, the average output current will ? ow through inductor l but is chopped between the internal top and bottom power mosfets. thus, the series resistance looking into the sw pin is a function of both the top and bottom mosfets r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 C dc) pgood voltage v out C8% C5% 5% 8% 3601 f04 0% nominal output figure 4. pgood pin behavior
ltc3601 16 3601fa the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance characteristics curves. thus to obtain i 2 r loss: i 2 r loss = i out 2 (r sw + r l ) 2. the internal ldo supplies the power to the intv cc rail. the total power loss here is the sum of the switching losses and quiescent current losses from the control circuitry. each time a power mosfet gate is switched from low to high to low again, a packet of charge dq moves from v in to ground. the resulting dq/dt is a current out of intv cc that is typically much larger than the dc control bias current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the internal top and bottom power mosfets and f is the switching frequency. for estimation purposes, (q t + q b ) on the ltc3601 is approximately 1nc. to calculate the total power loss from the ldo load, simply add the gate charge current and quiescent cur- rent and multiply by v in : p ldo = (i gatechg + i q ) ? v in 3. other hidden losses such as transition loss, cop- per trace resistances, and internal load currents can account for additional ef? ciency degradations in the overall power system. transition loss arises from the brief amount of time the top power mosfet spends in the saturated region during switch node transitions. the ltc3601 internal power devices switch quickly enough that these losses are not signi? cant compared to other sources. other losses, including diode conduction losses during dead time and inductor core losses, generally account for less than 2% total additional loss. applications information thermal considerations the ltc3601 requires the exposed package backplane metal (pgnd pin on the qfn, sgnd pin on the msop package) to be well soldered to the pc board to provide good thermal contact. this gives the qfn and msop packages exceptional thermal properties, compared to other packages of similar size, making it dif? cult in normal operation to exceed the maximum junction temperature of the part. in many applications, the ltc3601 does not dissipate much heat due to its high ef? ciency and low thermal resistance package backplane. however, in applica- tions in which the ltc3601 is running at a high ambient temperature, high input voltage, high switching frequency, and maximum output current, the heat dissipated may exceed the maximum junction temperature of the part. if the junction temperature reaches approximately 150c, both power switches will be turned off until temperature decreases approximately 10c. thermal analysis should always be performed by the user to ensure the ltc3601 does not exceed the maximum junction temperature. the temperature rise is given by: t rise = p d e ja where p d is the power dissipated by the regulator and e ja is the thermal resistance from the junction of the die to the ambient temperature. consider the example in which an ltc3601eud is operat- ing with i out = 1.5a, v in = 12v, f = 4mhz, v out = 1.8v, and an ambient temperature of 70c. from the typical performance characteristics section the r ds(on) of the top switch is found to be nominally 130m while that of the bottom switch is nominally 100m yielding an equivalent power mosfet resistance r sw of: r ds(on) top ? 1.8/12 + r ds(on) bot ? 10.2/12 = 105m.
ltc3601 17 3601fa from the previous section, i gatechg is ~4ma when f = 4mhz, and the spec table lists the typical i q to be 1ma. therefore, the total power dissipation due to resistive losses and ldo losses is: p d = i out 2 ? r sw + v in ? (i gatechg + i q ) p d = (1.5) 2 ? (0.105) + 12v ? 5ma = 296mw the qfn 3mm 3mm package junction-to-ambient thermal resistance, e ja , is around 45c/w. therefore, the junction temperature of the regulator operating in a 70c ambient temperature is approximately: t j = 0.296 ? 45 + 70 = 83.3c which is well below the speci? ed maximum junction temperature of 125c. board layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3601. 1. do the capacitors c in connect to v in and pgnd as close to the pins as possible? these capacitors provide the ac current to the internal power mosfets and drivers. the (C) plate of c in should be closely connected to pgnd and the (C) plate of c out . 2. the output capacitor, c out , and inductor l1 should be closely connected to minimize loss. the (C) plate of c out should be closely connected to pgnd and the (C) plate of c in . 3. the resistive divider, r1 and r2, must be connected between the (+) plate of c out and a ground line termi- nated near sgnd. the feedback signal, v fb , should be routed away from noisy components and traces such as the sw line, and its trace length should be minimized. in addition, rt and the loop compensation components should be terminated to sgnd. 4. keep sensitive components away from the sw pin. the r rt resistor, the feedback resistors, the compensation components, and the intv cc bypass capacitor should all be routed away from the sw trace and the inductor. 5. a ground plane is preferred, but if not available the signal and power grounds should be segregated with both connecting to a common, low noise reference point. the point at which the ground terminals of the v in and v out bypass capacitors are connected makes a good, low noise reference point. the connection to the pgnd pin should be made with a minimal resistance trace from the reference point. 6. flood all unused areas on all layers with copper in order to reduce the temperature rise of power components. these copper areas should be connected to the exposed backside connection of the ic. applications information
ltc3601 18 3601fa applications information 16 15 14 13 5 6 7 8 17 9 10 11 12 4 3 2 1 r2 via to v out via to pgnd r1 c fwd vias to intv cc vias to pgnd c in c out l1 sw c boost vias to pgnd c intvcc pgnd vias to ground plane vias to ground plane via to r2 v in v out 3601 f05 figure 5. qfn layout example
ltc3601 19 3601fa sw l1 c boost c out v out pgnd v in c in r1 3601 f06 r2 c fwd via to intv cc via to v out c intvcc pin 1 17 via to intv cc via to v out figure 6. mse layout example applications information
ltc3601 20 3601fa design example as a design example, consider using the ltc3601 in an application with the following speci? cations: v in = 12v, v out = 1.8v, i out(max) = 1.5a, i out(min) = 10ma, f = 1mhz because ef? ciency is important at both high and low load currents, burst mode operation is selected. first, the correct r rt resistor value for 1mhz switching frequency must be chosen. based on the equation dis- cussed earlier, r rt should be 324k. next, determine the inductor value for approximately 40% ripple current using: l = 1.8v 1mhz ? 600m a 1C 1.8v 12 v = 2.55h a standard value 2.2h inductor will work well for this application. next, c out is selected based on the required output transient performance and the required esr to satisfy the output voltage ripple. for this design, a 22f ceramic capacitor will be used. c in should be sized for a maximum current rating of: i rms = 1.5a 1.8v 12v C 1.8v ( ) 12 v = 0.54a decoupling the v in pins with a 22f ceramic capacitor should be adequate for most applications. a 0.1f boost capacitor should also work for most applications. to save board space the i th pin is connected to the intv cc pin to select an internal compensation network. the pgood pin is connected to v in through a 100k resistor. figure 7. 1.8v, 1.5a regulator at 1mhz applications information v in mode/sync run intv cc pgood ith rt ltc3601 pgnd sgnd boost sw v on fb track 2.2f c fwd 10pf c1 0.1f c out 47f v out 1.8v 1.5a r3 80k r4 40k 100k 324k c in : tdk c3225x5r1c226m c out : tdk c3225x5r0j476m l1: vishay ihlp2020bzer2r2m01 3601 f05 l1 2.2h c in 22f v in 4v to 15v
ltc3601 21 3601fa typical applications 12v input to 1.8v output at 4mhz synchronized frequency with 6v uvlo and 4.3ms soft-start ef? ciency vs load current v in run intv cc pgood ith rt ltc3601 pgnd external clock sgnd boost sw v on fb track mode/sync 2.2f 270pf 10pf 0.1f 10nf c out 22f v out 1.8v 1.5a 80k 40k 154k 40k 100k 80k 10k 3601 ta02a l1 0.68h c in 22f v in 12v c in : tdk c3225x5r1c226m c out : tdk c3216x5r0j226m l1: vishay ihlp2020bzerr68m01 load current (a) 0.01 40 efficiency (%) 60 90 80 0.1 1 10 3601 ta02b 20 30 50 70 10 0
ltc3601 22 3601fa 8.4v input to 3.3v output at 2mhz operating frequency using forced continuous mode ef? ciency vs load current v in run pgood track ltc3601 pgnd sgnd intv cc ith rt mode/sync boost sw v on fb 0.1f c out 47f v out 3.3v 1.5a r1 90.9k c ff 10pf r2 20k 3601 ta03a l1 2.2h c2 2.2f c1 47f v in 8.4v c in : tdk c3225x5r1c476m c out : tdk c3216x5r0j476m l1: vishay ihlp2020bzer2r2m01 load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3601 ta03b 30 20 10 0 90 100 typical applications
ltc3601 23 3601fa ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) 3.00 p 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 p 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 bottom viewexposed pad 1.45 p 0.10 (4-sides) 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 p 0.05 3.50 p 0.05 0.70 p 0.05 0.00 C 0.05 (ud16) qfn 0904 0.25 p 0.05 0.50 bsc package outline package description
ltc3601 24 3601fa package description msop (mse16) 0608 rev a 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 12345678 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 C 6 typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (note 3) 1.651 p 0.102 (.065 p .004) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop , exposed die pad (reference ltc dwg # 05-08-1667 rev a)
ltc3601 25 3601fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 4/10 changed temperature range for e-grade to C40c to 125c in order information sections updated note 2 updated pin functions updated functional block diagram updated equation in applications information section updated related parts 2 3 7 8 11, 15 26
ltc3601 26 3601fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0410 rev a ? printed in usa related parts part number description comments ltc3602 10v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4.5v to 10v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 4mm 4mm qfn-20, tssop-16e ltc3603 15v, 2.5a (i out ), 3mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 75a, i sd < 1a, 4mm 4mm qfn-20 ltc3604 15v, 2.5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 3.6v to 15v, v out(min) = 0.6v, i q = 300a, i sd < 14ma, 3mm 3mm qfn-16 and msop-16e packages ltc3605 15v, 5a (i out ), 4mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4.5v to 15v, v out(min) = 0.6v, i q = 2ma, i sd < 15a, 4mm 4mm qfn-24 ltc3610 24v, 12a (i out ), 1mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4v to 24v, v out(min) = 0.6v, i q = 900a, i sd < 15a, 9mm 9mm qfn-64 ltc3611 32v, 10a (i out ), 1mhz, synchronous step-down dc/dc converter 95% ef? ciency, v in : 4v to 32v, v out(min) = 0.6v, i q = 900a, i sd < 15a, 9mm 9mm qfn-64 typical application 1.2v output at 2mhz operating frequency v in run pgood track ltc3601 pgnd sgnd intv cc ith rt mode/sync boost sw v on fb 0.1f c out 47f v out 1.2v 1.5a r1 20k c ff 10pf r2 20k 3601 ta04 l1 1h c2 2.2f c1 22f v in 12v c in : tdk c3225x5r1c226m c out : tdk c3225x5r0j476m l1: vishay ihlp2020bzer1r0m01 ef? ciency vs load current load current (a) 0.01 40 efficiency (%) 50 60 70 80 0.1 1 10 3601 ta04b 30 20 10 0 90 100 v in = 8v v in = 15v

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